Are there any means to prevent PCB assembled with flawless IC chip from failing because of poor soldering?
IC Design houses test the quality of their IC products themselves but yet, PCB assembled with flawless IC component may still fail in certain cases. This not only a waste of time and money but also add additional costs for re-work and re-test. This is due to IC component makers’ lack of deep understanding on the causes and effects of packaging and bonding processes encountered by packaging and testing plants or system integrators on the final product manufactured. This disables them to meet the latters’ requirements as they know nothing about the technical aspects in making PCB. Here comes Board Level Reliability (BLR) aimed to make IC component fit its application environment more closely.
Also known as L2, Level 2 or Board Level 2, the board level process designed to mount L1 packaged IC onto PCB. BLR is a kind of test aimed to verify the reliability of solder joints of IC component mounted on PCB See Figure 1 for illustration.
This BLR, a standard verification test employed by the consumer electronics industry now, has been executed in iST labs for years. Amid rising complexity of vehicles’ electronic systems when more and more components and modules are employed, BLR is now a critical test required by most car electronic systems as well.
BLR is a MUST test item well-recognized amongst every senior semiconductor engineers. With increasingly more “new blood” injected into the semiconductor industry, iST has been being asked frequently by these new engineers for steps on doing the test, items covered by the test and ways to select test conditions. This iST Classroom documentation is aimed to help you learn more about BLR test.
1. What is the difference between consumer and automotive electronic BLRs?
(1) BLR verification for consumer electronics
The soaring complexity and process capability of consumer electronic goods mandate increasingly different kinds of IC chips. Take cellphone, to contain more and advanced chips in its applications, the structure of IC chip is moving in two directions. One is to compact individual chip as small and thin as possible, and the other is to combine multiple chips into one powerful chip. The latter will increase the dimension of IC component and change the packaging technology used which, in turn, requires the solder joints reliability of IC mounted on PCB to be re-verified again. To control and ensure the quality of components, leading consumer brands thus push IC chip suppliers to run BLR on their own. Critical items to be tested for IC-mounted-PCB for cellphone are mechanical and environmental stress like drop and temperature cycle respectively.
See JEDEC B102/ B103/A104/B111/B113 and IPC-9701~9704/9708 for international specifications on BLR for consumer electronic products, or, standards availed by leading consumer electronics brands.
(2) BLR verification for automotive electronics
With the increasing complexity of automotive electronic systems, more and more IC components are used in cars and therefore, BLR verification for car electronic components is now one of the critical tests mandated by car s makers. In addition to exclusive verification measures unveiled by Tier 1 car components suppliers, such as BOSCH, Continental and TRW, the Automotive Electronics Council (AEC) also explicitly defined TCT and drop tests in its BLR specification AEC-Q104 in 2018. Although covering only Multi-Chip Modules (MCM) instead of more common singular IC packaging types and apart from the customized specifications set by leading brands, the Q104 specification can still be counted as a big step forward in the general BLR requirement for car electronics. Amid booming car markets and global components shortage, the market is closely watching for the next revision release of Q104 by AEC. (Read more: Enter the Supply Chain of EV in Five Steps: An analysis of International Automotive Reliability Specs)
(3) Can BLR test conditions of automotive electronic products refer to or follow that of the consumer ones?
The answer is NO as these system modules adopted by car designs shall be subject to very different operating environments. Chips in vehicles are constantly under conditions of vibration, mechanical stress and harsh environment when on the road. Components meeting conditions of consumer products would fail quickly in a practical driving environment. See Table 1 for a summary of JEDEC and AEC-Q versus popular consumers’ specifications performed by iST .
Test Item A Company B Company C Company AEC-Q104 JEDEC RTC
. -40~125℃ @ 2,000cyc~4,000cyc
. 30 mins. Dwell time
. Dual chamber (Air to Air)
. -40~125℃, @mins. 2,000 cyc
. 10 mins. dwell time.
10 ≤ ∆T/∆t ≤ 20 K/min.
. 10 mins. Dwell times.
. 30 mins transfer time
Based on intended use environment
Based on intended use environment
PTC . -40~105℃ @ 2,600 cyc.
. T on/off =5mins
NA NA NA . -40~85℃
. T on/off =
20 or 30mins.
60 or 80mins./cyc.
Vibration . 100Hz~2,000Hz @ 5.02 PSD,
RMS acceleration: 97.7m/s2.
. Random Vibration + Temp.
. Real chip
. 20Hz~2,000Hz @ 0.1 PSD,
RMS acceleration: 189.4~818m/s2.
. Sine sweep or random VIB
NA NA 20Hz~2,000Hz
sine or random
Drop NA . Direction C+/C- :
. 1,000G, 1.4ms
. Direction C-
. 1,500G, 0.5ms, 60 drop
. Direction C-
. Direction C-
. 1,500G, 0.5ms, 30drop
Bending . Deflection
. Bend to fail
NA . Displacement
NA . Deflection
200k times or Bend to fail.
Table 1: Differences between specifications of consumers and international BLR
2. How to test BLR?
Design, fabricate and surface mount the BLR test board prior to proceeding with the BLR tests. Followed by post-test failure analysis to identify failure location and calculate the product life cycle. See Figure 2 for BLR flow and steps.
Figure 2: Steps for BLR test
(1) Step 1: Design and fabricate the PCB
The BLR test is aimed to determine solderability quality of component mounted on PCB. To do so, Step 1 is to design the daisy chain (Figure 3), a structure grid between every solder joints of your component and the PCB, to instantly monitor the yield of each joint and be informed as and when a joint fails during the tests. This is for development of any counteraction and improvement at the earliest, if any.
Figure 3: Daisy chain design
In addition to the JEDEC/IPC specification compliant PCB (Figure 4), iST also can develop your tailor-made PCB for your IC simulating those of your system integrators to effectively prevent unexpected situations.
Figure 4: JEDEC/IPC specification compliant test PCB provided by iST
(2) Step 2: SMT process
Surface mount your component onto the PCB is the second step for the BLR test. Quality of the mounting, including type of solder paste, demolding space, demolding time, printing speed, accuracy of component insertion position and selection of steel plate, will determine the accuracy of estimated product life cycle obtained from the test.
The SMT process will be followed by checking the reflow quality with X-ray or ultrasonic scan to determine the bonding status of solder balls.
As per iST’s experience, it is better to simulate the warpage of component and PCB before setting up SMT parameters for effective reliability assurance. This ensures good soldering yield during SMT, as well as prevents poor BLR verification and extra costs due to poor soldering quality.
The warpage measurement analysis is fast as it takes only about one hour to determine deformation of components under different temperatures. The simulated temperature cycling environment helps adapt to the BLR test later by detecting the temperature leading to the worst deformation (Figure 5) and useful in development of ways for prevention and improvements. (Read more: Count Warpage Amount Before SMT to Avoid Solder Empty and Early Failure)
Figure 5: Simulating temperature cycling environment to detect the temperature leading to the worst deformation
(3) Step 3: Run BLR test
The BLR test comes in two categories: low and high strain rate. Each of the two contains multiple tests aimed to find out robustness of solder joints to test boards under different conditions.
(4) Step 4: Total failure analysis after BLR test
Subject the BLR component mounted test board with identified failed joints from BLR test to board-level integrated failure analysis. This helps to quickly make any changes for re-verification after successful troubleshooting and to launch the product to the market as scheduled. To pinpoint defect with board-level integrated failure analysis, iST will do the following:
Detect joint defect with non-destructive 2D or 3D X-ray analysis
Detect delamination of component with non-destructive CSAM analysis
- Thermal EMMI:
Localization of specific defect location
- Dye and Pry:
Check for micro-crack of PCBA
Check specific area for cracks, if any (Figure 6 and Figure 7)
Figure 6: Cross-section on samples after high speed mechanical impact found crack at the joint of solder ball (marked by blue arrow)
Figure 7: Cross-section on samples after long-time hot-cool temperature changes found with cracks (marked by blue arrow)
3. Frequently found failures after BLR test
Here are three frequently raised questions in recent years.
(1) What does 1,000 temperature cycle test means for my product?
One thousand cycles equal to 1,000 days which, in turn, is nearly three years of operations. That means your product is most likely to work in its nominal application condition at least 2-3 years without defects, if it has gone through this test successfully.
(2) Which condition should I select for the mechanical impact (drop) test of BLR?
Different components would be employed for different applications. Cellphone, computer and tablet are unlikely to go through drop test at the same height. Take a cellphone, the height for its drop test is 112cm and the criterion you should choose is condition “B” of 1,500G, 0.5ms as shown in Table 2.
Service Condition Acceleration Peak Pulse duration Velocity Change Equivalent Drop height H 2900 g 0.3 ms 543 cm/s 214 in/s 150 cm 59 inches G 2000 g 0.4 ms 499 cm/s 197 in/s 127 cm 50 inches B 1500 g 0.5 ms 468 cm/s 184 in/s 112 cm 44 inches F 900 g 0.7 ms 393 cm/s 155 in/s 78.9 cm 31 inches A 500 g 1 ms 312 cm/s 123 in/s 49.7 cm 20 inches E 340 g 1.2 ms 255 cm/s 100 in/s 33.1 cm 13 inches D 200 g 1.5 ms 187 cm/s 73.7 in/s 17.9 cm 7 inches C 100 g 2 ms 125 cm/s 49.2 in/s 7.9 cm 3 inches
Table 2: Conditions for drop test
(3) How to estimate the service life of my product based on the data of BLR test?
You can estimate the characteristic life (η) of a product based on failure data of its samples from the tests with Weibull analysis. This can be used during the product’s verification or R&D stage to find out whether or not your product has sufficiently reliable service life.
See Figure 8 of a Weibull from a TCT test where Y-axis is the failure percentage and X-axis the time span of test. The characteristic life of substance 1 and 2 differs so much after 2,000 cycle tests. That is, the selection of materials plays a big role in BLR tests. A slight difference in the beginning may end up with major variance.
Figure 8: Material 1 (blue line): η = 3,506 cycles; material 2 (black line): η = 5,586 cycles