Where to seek help for CIS chip defects

Currently, there are three major types of CIS chip, including the (1) Front Side illumination (FSI), (2) Back Side illumination (BSI) and (3) Stacked CIS.

(1) FSI CIS

In order to manufacturing CIS chips by typical semiconductor process for mass production, FSI CIS (first type), the light sensing path receives light via the front side of the CIS chip, is designed and developed. However, the light interference from the metal layer above the image sensor is the fatal problem of FSI CIS performance, reducing the quantum efficiency and attenuating light sensibility of sensors.

(2) BSI CIS

Hence, BSI CIS was introduced to improve the light sensibility of CIS chips thereafter. By receiving light from the thinned backside of chips, down to a few micrometers, BSI CIS has significantly light sensing capability enhancement.

As for the BSI CIS process, the main difference lies in the additional wafer bonding and silicon substrate thinning down process, while both BSI CIS and FSI CIS adopt similar front-end processes. After the CIS process to form sensing diodes and backend metal routing, the front side of CIS wafer is bonded to a carrier wafer, which is the supportive structure to sustain the chip mechanical robustness after the thinning process of the backside CIS wafer. Then, backside grinding process is implemented on the bonded CIS wafer to thin the wafer to a few micrometers in order to enhancing light receiving efficiency. This is how the BSI CIS is made.

(3) Stacked CIS

With widely and boosting demands of consumer electronics applications, people are urged for higher image processing capability on their taking photos and videos with friendly product price. With the implementation of wafer stacking process, the CIS wafers can be processed by bonding CIS sensor wafers with mature process, ASIC wafers with advanced process for providing powerful computing capability, and even DRAM wafers together for a high-performance and cost-effective stacked CIS (Figure 1).

(1) To dig out the defect of hot spots with Thermal EMMI

When electrical failures, such as high resistance, short, leakage, or function failures, are found on a CIS chip, OBIRCH、Thermal EMMI(Figure 2), or InGaAs are well-selected and utilized for finding out the fault location by hotspot inspection based on different types of electrical failure modes, with applying DC power directly or testing pattern powered by test board, and facilitate the subsequent success Physical Failure Analysis (PFA).

● Timing for use of different types of equipment

(2) Layer-by-layer analysis on targeted dies

After fault isolation process, defect can be isolated on the light sensor, ASIC or DRAM chip, the Si substrate on non-interested side of the analyzed CIS chip can be removed first and then perform layer-by-layer process to reveal the physical of failure.

iST Failure Analysis Lab has successfully developed an unique solution to remove the unwanted parts of the CIS chip and expose the top metal layer (Figure 3) of the target area. With layer-by-layer removal and inspection, the burnout anomaly was found on Metal 1 (Figure 4) in this example.

(3) Electrical Characteristics Measurement (C-AFM and Nano-prober)

Besides of verifying electrical behavior through Voltage Contrast (VC) and inspecting the metal routing profile around the interested zone with SEM during the layer-by-layer removal, C-AFM analysis on the interested area can also be implemented to measure the electrical performance by obtaining the Current map (Figure 5) of that area in order to verifying if any leakage or open electrical faults can be observed.

If further electrical measurement and/or fault isolation are required on suspected defective paths after C-AFM analysis, Nano-Prober can be utilized for more accurate electrical fault isolation analysis, including Electron Beam Induced Current (EBIC), Electron Beam Absorbed Current (EBAC), and Electron Beam Induced Resistance Change (EBIRCH). (Further reading: Methods of precise positioning for defect detection based on nanoscale electrical characteristics measurement)

The Nano-Prober can also be performed electrical measurement on chips, such as obtaining the fundamental device characteristics (Vt, IdVg, IdVd, etc.) (Figure 6).

With the precise defect localization with the above methods, Dual-beam FIB or TEM can also be used to reveal the physical defects for further failure root cause investigation (Figure 7).

(4) Scanning Acoustic Tomography (SAT): Application on wafer bonding process of BSI/Stacked CIS chips

在Wafer bonding is a very critical process in BSI and Stacked CIS. In the wafer bonding process of BSI CIS and Stacked CIS, SAT is a powerful tool to detect if any bonding voids in-and-between the bonded wafers (Figure 9).