Issued Date：2020/6/10wafer ultra thinning
Issued By: iST
Compact power semiconductor is the hot topic now and is a future trend which, in turn, forced us to face and deal with the process risks that come with wafer thinning.
Wafer Ultra Thinning
Wafer ultra thinning has been the most direct and effective process improvement in cutting power consumption and input impedance of power semiconductors which not only reduce packaging dimension but also extends the service life of wafers by lowering RDS (on) and heat accumulation.
However, the MOSFET foundries are facing a challenge of balancing thinning and strength of wafers to minimize the risks of soaring rate of broken wafers.
iST has developed the thinning technology for wafers 2mil, 1.5mil, and even 10um thick. The silicon chips shown in Figure 1 are so thin that their surface may look lighting in red when exposing their backs to a white light source.
Figure 1: From Scanning Electron Microscope (SEM) results, the looks of 50um, 38um, and 10um thinned wafer
Let’s explore ways to improve the strength of thinned wafers.
I. In Terms of Wafer Grinding
An 8″ wafer die at initial thickness of 725 um (28.5 mil) may get thinned to 50 um (2 mil), 38 um (1.5 mil) or even 10 um (0.4 mil). The surface damage level by TEM analysis suggests that the depth of the damage layer goes along with grinding level (Figure 2) which result in mechanic stress accumulation, poorer die strength and a more demanding packaging and testing process. The iST exclusive optimized process is designed to deal with this challenge and raises production yield (Figure 2).
Figure 2: TEM maps of damage layers in blanket, 2mil and 1.5 mil wafers
II. In Terms of Wafer Etching
The wafer etching process not only gets wafer thinned but also strengthened by reducing stress accumulation at the damage layer by mechanic grinding as shown in Figure 3.
Figure 3: Increase wafer strength through etching process to reducing stress accumulation
The professional die strength test employed by iST optimizes the etching process to align the actual wafer strength with requirements set by customer specifications as shown in Figure 4.
Figure 4: Optimize the etching conditions to obtain higher strength and lower stress (HsLs) to facilitate following processing
iST can provide you with customized solutions to enhance your wafer for Power MOSFET/IGBT and other components. Should you have any inquiries, just ring Mr. Liu at +886-3-579-9909 EXT 5001 or email us at firstname.lastname@example.org