Issued Date：2022/5/3PCB Design
Do you know that PCB design is the key to pass or fail in broad level reliability tests?
We know that before coming to iST Reliability Test Laboratory for the Board Level Reliability (BLR) test, package design engineers must make a PCB in advance to simulate the potential solder balling problems when packaging components on a Printed Circuit Board (PCB). (Further reading: What does BLR mean for IC Design Engineers?)
During the experiment, when either the package or PCB fails, the reliability test will fail. Hence, a balance must be maintained between the package and PCB in order to optimize the life of the experiment.
When running a BLR test, however, besides ensuring that the PCB must meet the international specifications in terms of materials, thickness and routing layers, the PCB itself also affects the BLR test results. How should we design the PCB then? What knowhow is needed?
Also known as L2, Level 2 or Board Level 2, the board level process designed to mount L1 packaged IC onto PCB. BLR is a kind of test aimed to verify the reliability of solder joints of IC component mounted on PCB See Figure 1 for illustration(Figure 1).
Figure1: Solder Joints
I. How to start designing a PCB
1. Select reference regulations for the experiment
The BLR test falls into five categories: thermal cycling, vibration, drop, cyclic bending, and static bending. Except for thermal cycling which falls in the temperature change test group, all others are mechanical tests.
For consumer electronics, BLR tests can reference to international standards including JEDEC B103/ A104/ B111 /B113 IPC-9701~9704/ 9708 or the standards of individual leading brands of consumer electronics, including handheld products and automotive electronics, each brand has its own standards. While BLR tests can be run according to industrial standards or customer standards, it is necessary to first clarify the desired BLR testing standards before selecting the corresponding PCB specifications according to the test category.
Different testing standards have clear definitions of the material parameters, thickness, number of layers, routing layers, conductor width, via design, and surface finish. Some standards even define the stacking structure. Hence, careful design and production are required in order not to violate the standards.
2. Prepare packages and PCBs using the daisy chain design
While examining the quality of soldering joints is the purpose of BLR tests, it is necessary to form a daisy chain network with the soldering joints on the device under test (DUT) and PCB to perform real-time monitoring of the impedance changes. After determining if each solder ball fails and accurately capturing the failure time, we will understand the lifespan of materials and thereby make early improvement.
- What is a daisy chain?
A daisy chain circuit design can be divided into two sections: half of the circuit is designed on the package components and the other half on the PCB . After mounting the packaging components on the PCB with surface mounting (SMT), a complete daisy chain is formed.
Figure 2 Daisy chain design.
- What is a daisy chain?
II. What are the factors affecting PCB reliability in the BLR tests?
Based on our experience in running BLR tests for over one decade, we have concluded the following seven factors:
1. PCB pad side
Due to the stress generated by the test, the weakest position after PCB packaging will crack first. As shown in Figure 3a below, if the size of the package pad is larger than that of the PCB, the position near the PCB will crack first and vice versa. When the size of the package pad and PCB pad is consistent (Figure 3c.), stress distribution is the most even and better lifespan testing data will be obtained.
To achieve this goal, besides ensuring pad size consistency with the package in PCB design, the tolerance of the PCB maker should also be considered to ensure the PCB-package balance and thereby extend the test lifespan.
Figure 3: Impact of PCB pad size. In 3a, the package pad is larger, solder balls will easily crack first near the PCB. In 3b, the PCB pad is larger, solder balls will easily crack first near the package. In 3c, as the pad size of both the PCB and package is consistent, stress is even. Although solder balls on both PCB and package may crack, the time of complete cracking will be delayed.
2. Package pad distribution
If there are voids on the pad or pads are unevenly distributed on the package, there is risk of cracking due to uneven stress. The crack as shown in Figure 4 will mostly occur in positions without a pad.
Figure 4: Crack position
3. Routing layer
While different categories of tests bring different impact to the routing layer, it is necessary to select the correct routing layer according to the test category. For example, the common crack positions of thermal cycling tests will be different from that of mechanical tests. Hence, standard IPC 9701 requires that routing must be on the surface layer, while standard IPC 9702 specifies routing in the inner layer.
4. Package size
Package with a larger appearance is usually heavier, thus not suitable for mechanism tests. In addition, the package substrate will deform more easily after heating.
5. PCB warpage
There are four common causes of PCB warpage: (1) The coefficient of thermal expansion (CTE) of PCBs, therefore, warpage occurs more easily on PCBs making with heterogenous materials due to uneven contraction; (2) vias on different PCB layers may affect the amplitude of deformation; (3) the weight of the package on the PCB is also a factor of PCB depression, leading to a concave or convex PCBs after SMT; (4) uneven copper clad area on PCBs will deform the board due to thermal expansion. (Further reading: Count Warpage Amount Before SMT to Avoid Solder Empty and Early Failure)
6. Direction of DUT placement on PCB
DUT should be placed on the PCB based on it stress. In accordance with the requirements of JEDEC22-B111 and IPC9701, the packaging length and width should be consistent with the PCB outline.
7. Via locations
In addition to the restrictions in standards, pads with vias have better adhesiveness on BGA and better resistance against the pull of the complete pad than no via at all. The point is, vias must be filled with electroplating.
1. Which JEDEC version should be used? The new or the old?
Whether or not it is the previous version JEDEC- B111 or the new version JEDEC-B111A, it all depends on the size of the package itself, the cost and the testing items (as shown in Table 1 below).
Table 1: Application of old and new versions of JEDEC
2. Can different packages be loaded on the same PCB?
The answer is NO. Packages of different sizes and styles shall not be used on the same board, as this will affect the dynamic response of the board, making the results difficult to analyze.
3. Can different experiments be performed on the same PCB?
Can different experiments be performed on the same PCB? Can IPC 9701 TCT and IPC 9702 Bend be run on the same PCB? Based on practical experience of the iST BLR laboratory, PCB sharing is “not recommended.” This is because different tests have different rules and the part layout, PCB thickness and even routing layers may vary. Hence, PCB sharing may result in earlier failure of tests.
4. What is the best daisy chain design?
Dividing channels by pad distribution is the most commonly seen daisy chain design. This can benefit failure detection and defect analysis.
- Monitoring can be performed on one or multiple daisy chains. Channels are divided by pad distribution.
- The I/O of each daisy chain must be connected to the connector pin.
- All soldering joints on the package must be covered by the daisy chain, including the ground and power pins.
- Increase as many test points as possible to facilitate failure analysis when defects occur.