Issued Date：2021/7/65nm FIB
How can you maintain the electric integrity when editing 7nm or 5nm chips characterized by ultra-thin metal wires and space between them?
Thanks to Moore’s Law, the 10nm and 7 nm processes are now thinning into 5nm one. The iST’s FIB circuit editing lab has been contacted by clients to edit circuits from back side of samples by 5 nm process. After successfully edited samples of 7 nm process for the first time in 2018, the iST is now challenged to edit circuits of still more advanced processes to help clients in optimizing chip performances and shorten the product launch cycle. This iST classroom is to share with you the skills in editing circuits from the back side of chips by 7nm or even 5nm process based on years of exclusive experience.
The FIB electron microscope accelerates GA+ primary beam with an electric field into ion beams before hitting the sample surface to sputter secondary ions or electrons for imaging. By airing different gases when hitting the surface, the circuits would be edited as materials on chip surface are selectively etched at faster or slower speed and conductive and dielectric insulating materials are deposited to them. With the aid of the CAD navigation system and accurate positioning, the circuits are edited more precisely.
1. FIB, the Indispensable and Strategic Circuit Editing Technique for IC Design Houses
With rising costs in developing advanced processes and longer lead time caused by shortage in wafer production capacity, chips are more likely to miss the design target even when EDA and other circuit simulation software are getting better day by day. New masks for revised circuit not only cost more but also wastes more than one month for new chips to come out. Most IC design houses then choose to edit the IC circuits to ensure the latter’s compliance with the design specifications by spending fewer bucks and waiting for hours not tens of days.
2. Ultra-Narrow Space between Metal Layers in Chips by Advanced Process is a Great Challenge
This case of chip circuit editing is aimed to open the circuit for the M1 signal (see Figure 1) with the target area featuring the minimum metal pitch (MMP) and 4 signal lines in a space 218mm long. The metal layers on this chip, either 7nm or 5nm process, is no more than 10nm apart from each other. Such a circuit editing task is so challenging that our competitors have to give up.5nm FIB
See Figure 1 for an example of a poor editing case of chips by the advanced process where etching at the target point deformed (blue arrow marked), surrounding metal layers warped and deformed (yellow line marked) and multiple bottom layers exposed (white arrow marked). All these may damage or short the circuit and result in other electric anomalies which, in turn, threaten the rate of successful circuit editing.
Figure 1: Target point deformed (blue arrow marked), surrounding metal layers warped and deformed (yellow line marked), and multiple bottom layers exposed (white arrow marked)5nm FIB
Figure 2: Clear image, narrow spaces in between are visible, the area with etching removed is a tiny rectangle of dimension 40*100nm (yellow arrow marked) with lines on both sides remain intact; cutting at the yellow frame area would be much easier as neighboring lines are spaced farther apart.
To edit this advanced process circuit, iST cut the target point off with a very small rectangle of dimension 40*100nm (the yellow arrow in Figure 2). A more difficult challenge is the very limited space (up to 10nm) between adjacent metal lines; this is not only hard to cut but also demanding in maintaining electric integrity by leaving no damage to the neighboring structure. It would be much easier in case the metal lines on both sides are spaced apart even if their being on the same layer.
3. Editing Circuit on Chips of Advanced Process from Back Side
Chips made by the advanced process of single digit nanometers tend to be packaged by FCBGA or CIS-BSI (aka flip chip package) technology which layers a PCB Substrate on their front side. This mandates editing the FIB circuits from its back side. Doing this from the origin of the circuit would simplify the required operations and raise the success rate (see Figure 3).
Figure 3: Diagram for path tracking, let’s assume that this advanced process is 9M+AP. It’s very difficult to edit the M4 from chip’s front side as this requires going through 6 metal layers (AP~M5). Instead, editing from the back side not only reduces the number of layers to go through (just one Active Area layer) but also can simplify the editing on M1.
Back side editing comes with other benefits including lower aspect ratio, better imaging and precision and lesser editing time (see Figure 4 and 5).
In addition, shorter editing time would pile fewer electric charges by GA+ ion beams which, in turn, eliminates the risk of circuit damage and reduces errors caused by uncontrollable factors.
Figure 4: Back side editing is benefited with low aspect ratio as illustrated by the depth shown in the section view
Figure 5: The editing process shown in section view: mill the silicon substrate trench to expose the N well, editing the circuit at
4. Ready Your Weapon before Waging a War – the Most Advanced Tool for FIB Circuit Editing
FIB, a focused ion beam based circuit editing tool has been drastically evolving in image resolution, performances and precision along with the development of process in making chips. Aligned with the iST exclusive circuit editing skills, it is now mature in editing 5nm circuit from the back side. The latest equipment launched in Q1 (click here for its capacity) betters the insulation effects with higher resistivity (1E15 uΩ-cm) of dielectric material and challenges the more advanced process by raising image resolution from 4.5nm to 3.5nm and improving the success rate in editing circuits of very thin wires and greater complexity at a deeper location.