Home iST Latest Case Study in Die Bonding of Advanced Packaging

iST Latest Case Study in Die Bonding of Advanced Packaging

Home iST Latest Case Study in Die Bonding of Advanced Packaging

iST Latest Case Study in Die Bonding of Advanced Packaging

by edmund

Issued Date:2020/10/22Flip Chip Bonding
Issued By:iST

How to perform flip chip bonding on substrate with AI pad only?
How to prevent non-wetting or displacement when the copper pillar bump is replacing solder ball in the era of advanced packaging?

Flip Chip Bonding

Die bonding is getting critical to minimize packaging dimension while maintaining characteristics of ICs amid the era of 5G and the trend of compact end product design in spite of being just one of dozens of processes in their packaging operations.

The key point in die bonding is to employ the best technology and the least amount of media to mount dies on substrate at the exactly required position or stack them to the thinnest without any electrical distortion and pass the required reliability level.Flip Chip Bonding

Die bonding has been a manual operation in the past. Being a service provider for semiconductor verification and analysis, iST has employed an automated die bonding system last year to assist its customers’ verification tests and analyses in R&D stage to get bonding quality beyond the reach of manual operations. (Read more: “Automatic Die Bonding Technology: Ideal for Fast Engineering Sample Packaging“.)

iST will share with you a couple of die bonding technology cases in this iST Tech Classroom.

  • I. How To Perform Flip Chip Bonding On Substrate With AI Pad Only?

    The Under Bump Metallurgy (UBM) or Redistribution Layer (RDL) is frequently found in the last stage of wafer process: the Flip Chip (FC) packaging.

    During the R&D stage of ICs, it’s common to make samples by CyberShuttle to cut costs. However, some of them may fail to grow solder balls (due to lack of UBM or RDL layer) which, in turn, would hamper the electrical test over FC packaging.Flip Chip Bonding

    Addressing this issue, the iST quick assembly lab is capable to grow Au balls on AI pads before soldering them on to the substrate to facilitate wire bond (W/B) or FC packaging verification for chips with AI pad only (Figure 1).

    AU Ball Flip Chip Bonding

    Figure 1: Grow gold balls on AI pads before soldering them on to substrate

  • II. How to Prevent Non-Wetting or Displacement When the Copper Pillar Bump is Replacing the Solder Ball (these Two Differ in Nature from Each Other) in Small-space FC Packaging?

    Amid shrinking packaging size, mounting of FC packaging requires an increasingly demanding alignment accuracy while solder balls are getting replaced by copper pillars with the latter spaced less than 150um apart.

    Increasingly diversified materials of bumps for FC packaging is complicating the control over soldering temperature profile (Figure 2).

    temperature profile Flip Chip Bonding

    Figure 2: Increasingly diversified materials of bumps for FC packaging requires not only more accurate alignment system when mounting but also more demanding soldering temperature profile

    In addition to the mechanic, electric and passive cooling features offered by conventional solder balls, its copper pillar bump counterparts are giving better cooling, conduction and anti-electronic migration capacity; low resistance, induction and thermal resistance; smaller space in between bump contacts to face the challenges set by end products with a compact design today.

    These extra features bring along better signal communication capacity and reliability. That is, copper pillar bumps are enabling more complex IC packaging (e.g., 3D IC) for the development of more integrated systems with robust functions in micro and precision footprints.

    Differing from the solder balls’ larger solder spots, the space in between copper pillar bumps is usually no more than 150um apart. The former can then go with larger displacement and temperature profile which enables making samples by manually mounting them to the substrate with hot air gun or heating pan.

    The tin on copper pillar bumps is 20-50 um thick. Heating them with a hot air gun or hot plate tends to result in non-wetting or displacement. Bonding them then requires a more precise alignment system and smaller soldering temperature profile.

    However, most scale packaging factories tend to reject the services for copper pillar FC die bonding orders of low-quantity-high-diversification in R&D stage. Addressing this issue and assisting customers in sample preparing during R&D stage, iST is debuting its copper pillar bump services for orders of low-quantity-high-diversification. See Figure 3 for operating flow.

    flip chip bonding

    Figure 3: Copper pillar die bond operation flow

  • III. How to Conduct Eutectic Die Bonding

    Also called eutectic die attachment, the eutectic die bonding is designed for die bond packaging process requiring good heat dissipation and reliability in making high power amplifiers and LEDs.

    Small amount of engineering sample dies bonded by adhesives can be made by manual die bonding operation. This is not the case with eutectic die bonding as it requires temperature profile and pressure to bond two different metals together. An automated equipment along with given process is required as shown in cases below.

    (i) Die Bonding with Solder Preform

    A “solder preform” is a piece of solder pre-fabricated into required dimension and geometry. Die bonding with solder preform mandates given temperature profile and pressure. The end product may sufer poorer reliability due to gaps in between dies and substrate by rough surface of the solder preform and substrate during die bonding. The iST quick assembly lab is recommending to use the scrubbing technology to remove gaps caused by solders with flows as shown in Figure 4.

    Solder preform die bonding flow

    Figure 4: Solder preform die bonding flow

    (ii) Reverse Mounting Dies then Solder the Pad to the Substrate

    In case of gold surface of die pad, the thermosonic process is employed for the gold-nickel bonding process to lower operation temperature and prevent poor eutectic caused by oxides on metal surface. Addressing this issue, the iST advanced packaging lab is adding nitrogen, an inert gas, in the heating zone and employing thermocompression along with exclusive parameters, including temperature profile and pressure, to mitigate oxidation of metals in high temperature environment. The process may get connected with the iST failure analysis lab to check soldering quality by X-ray or die shear test. See Figure 5 for the operation process.

    Flip Chip Bonding

    Figure 5: Au-NiAu bonding process

  • IV. How to Sort Dies into Wafer Frame Successfully?

    Chips cut from one wafer may be delivered to different contractors or labs. Each batch of chips are sorted by operators (in given quantity) and delivered with waffle pack. A special case occurred to the iST quick assembly lab where the equipment of the contractor can be loaded with chips by wafer frame only. That is, dies can be delivered only with the latter.Flip Chip Bonding

    It’s very difficult to manually sort dies to wafer frame at given position. The automatic equipment of iST enable the customer to place dies on the film of wafer frame at given space and layout to enable required tests later (Figure 6).

    Figure 6: Mounted wafer frame (inset of dies shown on the right hand side)

In case you need more information of engineering sample packaging and customized packaging requirement, please contact Mr. Benson Yang at 886-3-579-9909 ext. 6862 │ Email: ist_assy@istgroup.com

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