FIB Microscope employs liquid metal ion source (LMIS) of gallium which irradiates the sample surface to obtain images or remove impurities. The method is similar to FESEM (Field Emission Scanning Electron Microscope), except that FIB Microscopy uses gallium ion to hit the sample surface. Combining with successful selective etching of organic gas and deposition of conductors or non-conductors, the FIB Microscope is mainly used for IC circuit edit, partial cross-section, and crystalline phase analysis.
IC Circuit Edit is one of the most beneficial applications of FIB. Due to the merit of saving a mask redo, FIB significantly shortens time for IC prototype validation and Time-to-market, which is a substantial advantage in IC design. FIB provides selective etching and deposition of conductors or non-conductors at a micrometer scale or even nanometer scale, offering IC designers opportunities of direct modification of circuitry that enables layout verification and saving both development time and modification costs.
iST always stays ahead on the equipment specification and capacity of FIB by owning the highest level of equipment, FEI V400ACE which is intended for the front-side and back-side circuit edit of 20nm process. Furthermore, iST built two upgraded equipment of FEI 986-IET, which perform precisely on 28nm process, and enable on-chip FIB applications directly on 8” wafers.
iST provides more than 20 FIBs in total, and has advantages in terms of yield and capacity. Our FIB lab works 24-7 around the clock every day, and is committed to return the samples in 24 hours.
Features of FIB Laboratory
Minimum operation on 20nm metal-1 with 4.5nm resolution.
Maximum applicable to 8” wafers.
Supports Knights Merlin CAD Navigation.
Precision laser guided platform.
Infrared microscope for observing CMP layer and isolating silicon layer.
Conductor metal is platinum (faster) or tungsten (low resistance).
Proposals for improving circuit editing results
Before FIB, test once more after glue removal, wire bonding or packaging.
Yield decreases if multiple alterations are made on the same IC.
The resistance of conductor metal by FIB is higher than the original. Any low resistance conductor demand, please specify it on the commitment form.
Suggest providing GDSII circuit layout to facilitate navigation (partial area or layer will be fine), this can help increase the yield.