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IC Delayer Process
 

Principles:
Remove the multi-layer structure of the chip (passivation, metal, IDL) by repetitive combination of different approaches (ion etching/ chemical etching/ mechanical polishing), to enable layer-to-layer observation or photo-taking of internal defects.

Applications: 
   Failure analysis: identify defects through layer by layer inspection.
   Circuit Reverse Engineering: Clearly resolve multi-layer circuit structures through IC delayer process and following photo-taking.

Machine / model ﹕
   Trion Ion Etching Machine
Example photo of IC Delayer
 
M1 (OM photo )
 
M2 (OM photo)
Example photo of IC Delayer 
 
POLY(OM photo)
 
Poly / Contact (SEM photo)
delayer、polishing、lapping
吳先生/Sam
+886-3-5799909#6736
web_decap@istgroup.com
Please contact nearest location for inquiries :
USA Taiwan ─ Hsinchu China ─ Shanghai Kunshan Beijing Shenzhen Japan
Other services you may be interested in:
 
FIB Circuit Edit
IC Backside Polishing
IC Reverse Engineering
IC Cost Analysis
Scanning Electron Microscope(SEM)
Nano Prober
IC Decapsulation
 


 
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