It sometime occurs that root cause of failure cannot be identified no matter what means has been used in an IC failure analysis; however Delco engineers have found an answer in the laboratory.Delco engineers found that when the IC circuit is in a high-temperature and high electric field environment, a parasitic capacitance will be carried between the Molding compound and the Die, forming accumulation of electric charges which may induce leakage of a logic gate, causing a malfunction of the IC. These anomalies will disappear, however, when the IC has been desoldered from the PCB, baked in a high-temperature oven, and decapped.
In general practice, temperature of lead-free process is 30°C~40°C higher than a tin-lead process, thus forms a high-temperature environment.In order to meet requirements of the high-temperature lead-free assembly, SMT machine suppliers responded by increasing the Heating Zone and heating energy of the machine. This worsens the electric field environment than the past, gradully increases gate leakage in the IC induced by the high temperature and high electric field.
Along with successive advances in recent years, complexity in IC processes escalates continuously; added with countless Die Shrinking efforts made by IC design companies for expanding application range and lowering costs, the probability of Gate Leakage problem has therefore increased significantly.Some researches show that Gate Leakage is mostly seen in high-voltage components; the percentage of leakage in vehicle electronics which work in a high-voltage/ high-temperature environment is even higher, therefore the Automotive Electronic Council has incorporated Gate Leakage Test as a mandatory item for IC Reliability Test.
Besides years of experiences in IC Reliability tests, iST has successfully developed capabilities for setting up high-temperature / high electric field induced Gate Leakage Tests in the current year all by its own, and is ready to provide test services to domestic and overseas customers. Entrusted tests are welcome for all customers, old or new. We will be more than happy shearing experiences with you.
Set-up and procedures of the test
AEC-Q006 Electro-Thermally Induced Parasitic Gate Leakage Test (GL)
The failure theory
Cross-section of a dual metal circuit and the equivalent GL circuit
||The characteristic curves of an input pin exposed to and degraded by GL|
ISTFA '93: The 19th International Symposium for Testing & Failure Analysis, Los Angeles, California, USA / 15-19 November 1993