The IC Operating Life Test simulates a long-period of work environment with accelerated temperature and voltage alterations in a short period of time, in which the Bathtub Curve is divided into 3 sections namely Infant Mortality (Early Life Failure), Useful Life, and Wear Out. Different test methods are applied for different failures.
Most common Operation Life Test methods are:
BI (Burn-in) / ELFR (Early Life Failure Rate)
For assessing failure rate in the Early Failure section, or for reducing Early Life Failure Rate via the Burn-in approach. The rate is indicated by DPPM (Defect Parts Per-Million)
HTOL(High Temperature Operating Life)
For assessing the span of operating life, indicated by FIT or MTTF.
TDDB (Time dependent Dielectric Breakdown)/HCI (Hot Carrier Injection) /EM (Electromigration) tests for assessing life performance in the Wear Out section.
There are also test methods and test conditions corresponding to different product categories, such as HTGB (High Temperature Gate Bias) / HTRG (High Temperature Reverse Bias) / BLT (Bias Life Test) / IOL (Intermittent Operation Life).
All the above test conditions require a power supply or signal source to activate the element into working condition or stability. Cycling alteration of Acceleration Factors (voltage and/or temperature) is imposed to the sample for aging effects, the test results are used for calculating the failure rate, FIT (Failure In Time) and MTTF (Mean Time To Failure).
One of the most popular topics in recent years is the Fault Coverage over the IC Operating Life. Experiments are carried out with the burn-in system with memories in depth, by increasing the toggle rate of the logic gates in the IC in a fixed test time. Reliability of the IC Operating Life Test increases when the Fault Coverage increases.
MIL-STD 883 / MIL-STD 750
JESD 47 / JP001.01 / JESD22A-108 / JESD 85 / JESD74 / JEP122
AEC-Q100 / AEC-Q101