Home 【Ctimes】iST TEM Material Analysis Technique Hit 5nm

【Ctimes】iST TEM Material Analysis Technique Hit 5nm

Home 【Ctimes】iST TEM Material Analysis Technique Hit 5nm

【Ctimes】iST TEM Material Analysis Technique Hit 5nm

by ruby

Issued Date: 2016/6/8
Issued By: Ctimes

Amid further advanced processes pursued by the semiconductor industry, iST is announcing its breakthrough in material analysis (MA) test techniques today (June 8). Its TEM material analysis technique is now accepted by international customers for 5 nm process verification.

iST is not only assisting customers in TEM analysis and verification for their products by advanced processes, but also is being recognized by International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), the leader in the field of IEEE semiconductor components failure analysis, with research papers reviewed and presented successfully in its forum in consecutive years.

Aiming at achieving higher performance, lower power consumption, and more compact semiconductor components to meet the demands of smart products today, leading industry players are accelerating their advanced process development. In the wake of 20 nm before last year and 14 nm one year later, 10 and even 7 nm mass production debuts this year, many semiconductor suppliers are eyeing the R&D of the 5 nm process. This is to mandate material analysis requirements throughout the entire supply chain, observed iST.

Material analysis is key to iST’s investment lately. iST has doubled its production capacity in the last three years. After acquiring the material analysis technique of 10 nm late last year, it has been contracted by heavy weight semiconductor clients, said iST.

The 5 nm process will be the next battlefield of wars waged by individual semiconductor manufacturers. iST is playing the best pushing force in advancing the production process with testing and verification solutions, noted PhD. Sheng-yu Chen, material analysis director of iST. At least one international semiconductor customer marching towards the 5 nm process is being serviced by iST with 24-hour non-stop operation for verification and analysis with its high-end equipment and techniques.

Sheng-yu Chen points out that non-miniature processes are getting attention by the industry as processes narrower than 5 nm will hit the wall of physical limitation faced by Moore’s Law. 3D IC is one of the most eye-watering solutions. The paper “Novel TEM applications to characterize through-silicon vias” presented in IPFA suggests a whole new mechanism addressing analysis mandated by 3D IC process.

In any 3D IC process, thermal stress is a critical issue and must be subject to precision control to maintain in acceptable range and ensure product reliability. The paper released by iST employs new TEM analysis techniques to identify stress distribution in 3D IC process structures up to single digit nm. This is poised to help break stress analysis limits suffered by customers in the past, added Sheng-yu Chen.