Introduction
Amid the reshaping of global semiconductor supply chains and continued industry growth,
Penang is rapidly strengthening its position as a key semiconductor manufacturing and engineering hub.
As more semiconductor products move from development to qualification and production,
engineering teams often face critical roadblocks: delayed test hardware interfaces and sample preparation after wafer out,
gaps in transitioning from component-level qualification to Board-Level Reliability (BLR),
complex FA cases requiring cross-border support—all of which can significantly slow down time-to-market.
With over 30 years of excellence in semiconductor validation and analysis, Integrated Service Technology (iST) is hosting an in-person technical seminar in Penang, bringing Taiwan’s proven semiconductor engineering and validation experience to Malaysia to support faster development and stronger local engineering capabilities.
Senior engineering experts from Taiwan will share proven industry methodologies spanning wafer out, test interface design, reliability qualification from CLR to BLR, and in-depth root cause failure analysis.
The session will also touch on key qualification requirements such as AEC-Q where applicable, helping Penang’s engineering and quality teams strengthen end-to-end validation capabilities—from chip-level debugging to global compliance—and accelerate development cycles.
Workshop Highlights
• Accelerate the path from wafer out to validation
• Improve test efficiency with the right test interface solutions
• Strengthen reliability from component to board level
• Identify failure mechanisms and root causes faster
• Reduce revalidation and compliance risks
Event Schedule
| Time | Topics | Speakers |
|---|---|---|
| 09:00-09:30 | Registration | |
| 09:30-09:35 | Welcome Remarks | Integrated Service Technology Inc. Sales Director Kerry Chien |
| 09:35-10:00 | Accelerating Silicon Validation – Reduce Development Cycle & Time-to-Market | Integrated Service Technology Sdn. Bhd. Sales Manager Alvin khoo |
| 10:00-10:30 | From CLR to BLR: A Complete Reliability Validation Solution from Component to Board Level | Integrated Service Technology Inc. Senior Vice President of Reliability Analysis Engineering Allan Tseng |
| 10:30-11:30 | From Wafer Out to Fast Validation | Integrated Service Technology Inc. Senior Vice President of Reliability Analysis Engineering Allan Tseng |
| 11:30-12:00 | TBD | Inviting |
| 12:00-13:30 | Lunch & Networking | |
| 13:30-14:30 | Key of Semiconductor Excellence: Failure Analysis (FA) Introduction and FA Capability in iST | Integrated Service Technology Inc. Director of Failure Analysis Engineering Dr. Sean Shen |
| 14:30-15:00 | From Design to Market: De-Risking Product Compliance Through Early Testing & Certification | QAV |
| 15:00-15:20 | Coffee Break | |
| 15:20-15:50 | ˙Thermal Solutions ˙Crest Tester ˙Laser Cleaning Machine | Contacthings |
| 15:50-16:20 | TBD | Inviting |
| 16:20 | Networking & Adjournment | |
Workshop Information
Target : Professionals in IC Design, Foundry, OSAT, R&D, Test, Reliability, FA, and Quality Engineering.
Fee: Free
Time: 2026/10/20 (Tue) 09:00-16:20
Venue: Level 4 Jadeite, Amari SPICE Penang
Address: 8 Jalan Mahsuri Mukim12, Bayan Lepans, Penang
Parking Information: B1-B2, Amari SPICE Penang
Parking fee: RM5 per entry, with no time limit.
Contact:
Ms. Samantha Phoon, Mobile : +60164737418
E-Mail:samantha_phoon@istgroup.com
Organizer
(iST) Integrated Service Technology Inc.
The organizer reserves the right to adjust or change the agenda. The final agenda is subject to the on-site arrangement.
To protect the intellectual property rights and confidential information of the speaker, presentation slides will not be provided for this workshop.
Limited spots are available. All registration applications will be reviewed before your registration is confirmed. Successful applicants will receive a confirmation email.