iST Introduces Low Temperature Soldering Process to Reduce Warpage Deformation

In view of the recent soaring frequency of warpage-relevant non-wetting reliability issues after SMT (Surface Mount Technology) process of hetero-integrated chips, which caused the early failure in subsequent reliability tests. iST announces today (July 27, 2021) that it is introducing the Low Temperature Soldering (LTS) process, which subjects samples of small-size WLCSP with heterogeneous alloys soldering by LTS process for subsequent reliability verification. The result of temperature cycle test (TCT) shows that samples by LTS process rival their Pb-free counterparts and this may help customers reduce the level of warpage deformation.

As the “System in a Package” has become a current trend, integrating ICs of different materials usually containing substances with varying coefficient of thermal expansion (CTE) and functions into one package, which will lead to warpage by stacking complex and diversified packaging components. This has been the greatest challenge faced by raising the yield of the SMT, iST observed. Regarding warpage-relevant non-wetting, the conventional method is to cut the probability of warpage-relevant non-wetting by adjusting the design of solder paste’s stencil and reflow temperature based on results of warpage simulation. iST has been assisting many clients in successfully dealing with the soldering issues of PCBs or IC warpage.

However, the aforementioned method, preventing non-wetting or short circuit by applying correct amount of solder pastes, doesn’t work when the level of warpage gets higher. Regarding this issue, iST’s BLR lab introduces the new method of LTS process to reduce level of warpage deformation with less thermal stress.

iST pointed, warpage is the results of deformation by soldering substances of different CTEs when stacking ICs made of different materials. The higher the temperature is the IC package will suffer more deformation by thermal stress. Lower SMT soldering temperature would reduce thermal stress significantly which, in turn, would not only reduce warpage suffered by PCBs and components but also cut the energy consumption. The melting temperature of tin, silver, and copper alloys used by most Pb-free processes is about 220℃ (with peak values falling in the range 230℃~250℃) while that of tin and bismuth alloys used by LTS process is 140℃ (with peak values falling in the range 170℃~200℃).

iST further pointed, LTS process is prone to hot tearing phenomenon because of the different melting temperatures required for different alloys. By precision control of temperature and solder paste volume, iST’s BLR lab is able to prevent hot tearing encountered by the LTS process (see Figure below).

LTS process remains an acceptable method to reduce warpage as long as the CTE issues cannot be solved by packaging materials. The actual application may include other active and passive components such as chip resistors, capacitors, memories, and transistors. All of them should be ready at the earliest for quick products launch, iST said.

About Integrated Service Technology

Founded in 1994, iST began its business from IC circuit debugging and modification and gradually expanded its scope of operations, including Failure Analysis, Reliability Verification, Material Analysis, Automotive Electronic Verification Platforms and Signal Integrity Testing Services. iST has offered full-scope verification and analysis services to the IC engineering industry, its customers cover the whole spectrum of the electronics industry from IC design to end products.

In response to rising Cloud Intelligence, Internet of Things (IoT) and Internet of Vehicles (IoV), iST not only focuses on its core services but is also expanding its service offerings based on international trends, such as automotive electronic verification platforms, signal integrity testing services.http://www.istgroup.com