Issued Date: 2019/5/9
Issued By: iST
After iST rolled out the previous video about our fab discovery-how to make a flimsy wafer? The Taiko grinding process. Questions have been pouring in; many customers would like to know further about the thickness limit of wafer thinning, and the procedure of MOSFET wafer thinning. As well as the present demand on the market, future development and how iST could assist customers in solving problems?
This month, we will continue inviting Tony Liu, the R&D director of iST and a master of surface process engineering in semiconductor manufacturing to answer your questions with 2’40” quick-quiz video, quickly solve all kinds of your doubts! Let’s Go!
Other Related Topics:
iST’s Wafer Backend Process is Now IATF 16949 Certified
Electro-less Plating –Your High CP Value Choice for MOSFET FSM
Sputtering Deposition V.S. Electro-less Plating: Two Options for MOSFET FSM
How to Quickly Reduce MOSFET RDS(on) Without Changing Your Design
iST Officially Enters MOSFET Wafer Backend Process Integrated Services