Home Determining Whether IC Defects are Caused by the Poor Packaging

Determining Whether IC Defects are Caused by the Poor Packaging

Home Determining Whether IC Defects are Caused by the Poor Packaging

Determining Whether IC Defects are Caused by the Poor Packaging

by ruby

Issued Date: 2018/3/27
Issued By: iST

IC short circuits vanish after decap.
They may have been caused by the package defects, but how to find the root cause?

You have probably encountered this all too often as an IC design engineers: suspecting your circuit design leads to power leakage and short circuits, among other defects, you have iST decap your ICs for electrical measurement including InGaAs, EMMI, and OBIRCH. After decap, all defects vanish into thin air. At this point, you may be relaxed as you are not at fault but worried at the same time since you still need to find the source of the defects.

Most likely it’s the poor process of the IC package, which is the source of the trouble.

In general, to identify IC defects we damage its package by decap or compound removal. However, this is not the case with package defects, as destructive inspection would damage the target you need to examine.

The iST Tech Classroom for this month is about finding ways to pinpoint IC defects without damaging the sample itself.

three-steps-by iST assist you catching defects
Step 1: Positioning

Detect failure depth (Z-axis direction) of IC packages with Thermal EMMI by phase differences of thermal radiation at the failure point without damaging powered IC devices to quickly position the failure point (getting its XYZ coordinates) and, in turn, concluding that the hot spot falls at the wire bonding area of the package rather than the body of die 2 (see figure 1 below).

Figure 1: Image by Thermal EMMI

Step 2: Imaging ←→ position repeatedly to narrow down and pinpoint defect positions

Without destroying the device, the 3D X-ray system presents an image at the failure position in a 3D view to find any abnormal hot spots in the area located as shown in figure 2; if no visible defects are found, then subject the sample to further processing before performing positioning analysis again to highlight relevant abnormal hot spots for later analysis as shown in figure 3.

Figure 2: Detect the relevant positioning area with a 3D X-RAY and find no visible defects

Figure 3: Positioning again with Thermal EMMI to highlight relevant abnormal hot spots for later analysis

Step 3: Slicing

Slicing tools of low stress are needed here, as the bill of materials (BOM) of IC components typically suffer from weaker stress resistance. Conventional manual grinding may damage the sample due to the heavy stress applied. Instead, slice the cross section of defect with a low stress Plasma FIB to pinpoint potential causes. It turns out that the package contains metallic substances, magnesium (Mg) and aluminum (AI), which should not exist here. This leads to abnormal leakage by the package as shown in figure 4. This also tells us why the 3D X-ray failed to find abnormal hot spots in Step 2, as they pass through loose metals including magnesium and aluminum instead of imaging them.

Figure 4: FIB X-S suggests IC electric abnormality is caused by Mg and Al content in the package.

This article aims to share our detection and verification experiences with clients like you. Should there be any difficulties in IC failure analysis or you would like to know more about the aforementioned techniques, please call Mr. Fang at +886-3-579-9909 Ext. 8585 or email him at web_ise@istgroup.com.