Along with successive advances in recent years, added with countless Die Shrinking efforts made by IC design houses for expanding application range and lowering costs, the probability of Gate Leakage problem has therefore increased significantly. Some researches show that Gate Leakage is mostly seen in high-voltage components; the percentage of leakage in vehicle electronics which work in a high-voltage/ high-temperature environment is even higher. Through this test we can understand the reaction of the devices under a high electric field.
When the IC circuit is in a high-temperature and high electric field environment, a parasitic capacitance will be carried between the Molding compound and the Die, forming accumulation of electric charges which may induce leakage of a logic gate, causing a malfunction of the IC. These anomalies will disappear, however, when the IC has been desoldered from the PCB, baked in a high-temperature oven, and decapped.
In general practice, temperature of lead-free process is 30°C~40°C higher than a tin-lead process, thus forms a high-temperature environment.In order to meet requirements of the high-temperature lead-free assembly, SMT machine suppliers responded by increasing the Heating Zone and heating energy of the machine. This worsens the electric field environment than the past, gradully increases gate leakage in the IC induced by the high temperature and high electric field
The characteristic curves of an input pin exposed to and degraded by GL.
Degraded and soft knee
The Superiority of iST
- Extensive experience: as the leader in providing this test in Taiwan, iST is the best expert with real test experiences.
- Standard operation procedure: provide SOP to ensure the test quality.
- AEC-Q100-Rev-G Electro-Thermally Induced Parasitic Gate Leakage Test (GL)
- Automotive electronics