Remove the multi-layer structure of the chip (passivation, metal, IDL) by repetitive combination of different approaches (ion etching/ chemical etching/ mechanical polishing), to enable clearly presenting circuit layout structure of each layer for later experiments.
The Superiority of iST
IC delayer → OM reviewing → Contact layer scanning (VC) with SEM high and low voltage→ etching to gate oxide then view by SEM
IC delayer to Contact → OM viewing and imaging →SEM electronic and secondary electronic scanning → polishing to poly → SEM scanning to get Poly Profile
FinFET process delayer to Substrate → OM viewing and imaging →SEM scanning
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